Design Verification Engineering
Verification & Front-end ASIC Design flow Engineer
Expinfo provided technical support for development and deployment of flows and methodologies for Functional Verification (Testing) & Front-end Design of high performance SoCs (System on Chip), trouble shooting, and debugging of issues related to tools and flows used in Design & Verification flows and helped in flow enhancement to achieve standardization of IP design and re-use.
Worked as clearecase database manager to setup & support standardize chip development UNIX environment with required technology libraries, flows & tools installation, update and maintenance. Used tools and languages like C, Perl, TCL, Unix & ClearCase.
Design Verification Engineer
IP & Chip functional verification by developing test plan from specification, testbench creation including components like constrained random vector generator, BFM, driver, monitor, behavioral model, checker & scoreboard, achieving code coverage & functional coverage, test case generation, test regressions and debugging Have done verification of an ALU, IP forwarding Engine, Networking router with Lookup table and DMA as well as top level DSP using Verilog, Perl, C, Assembly, Specman & UNIX.
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